The present invention relates to semiconductor device testing, and more particularly to detecting failures and failure mechanisms in semiconductor integrated circuitry, especially CMOS (Complementary Metal-Oxide-Semiconductor) integrated circuitry.
As semiconductor devices (e.g., CMOS integrated circuits) become increasingly complex, it becomes increasingly difficult, and increasingly important, to identify elements of those devices that affect common failure modes and “critical parameters” of the device. Typically, critical parameters are “spec sheet” performance limits that dictate whether a completed device meets or fails to meet its target specifications. Examples of such limits are critical setup times, hold times, min/max propagation delays, etc. Other examples include min/max voltage levels at a given drive current, min/max slew rates or rise/fall times (usually determined by comparing a voltage against predetermined threshold levels before and after a predetermined time interval), etc.
A variety of techniques employing laser scanning have been used to induce and detect anomalies in complex semiconductor devices via thermal stimulation or photon bombardment. It is well known to those of ordinary skill in the art that thermal stimulation and/or photon bombardment can be used to affect the behavior of semiconductor devices. For example, U.S. Pat. No. 5,430,305, “Light-induced Voltage Alteration for Integrated Circuit Analysis”, issued Jul. 4, 1995 to Cole, Jr. et al. (hereinafter “Cole '305”) describes a prior-art technique whereby LIVA (Light Induced Voltage Alteration) is employed to sense voltage changes across a semiconductor device driven by a constant current source. These voltage changes occur in response to a focused, scanning light source (e.g., a laser scanning microscope (LSM)). In one embodiment of Cole '305, the voltage changes are used to produce a light dark image that is synchronized with and overlaid upon an “visual” image of the device under test (DUT) to produce a visual on-screen indication of the state of the sensed voltage changed at the time when the scanning beam passed over the corresponding location on the DUT.
Another example of a prior-art technique is given in U.S. Pat. No. 6,078,183, “Thermally-induced Voltage Alteration for Integrated Circuit Analysis”, issued Jun. 20, 2000 to Cole, Jr. (hereinafter “Cole '183”) describing a technique whereby a laser microscope (or similar device) is used to scan a semiconductor device. The scanning beam produces localized heating of conductors (e.g., patterned metallization) of the semiconductor device. This localized heating produces a thermoelectric potential due to the Seebeck effect in and conductors with open-circuit defects and induces a resistance change in any conductors with short-circuit defects. In either case, this produces a voltage change across the semiconductor device when powered by a constant current supply. The voltage across the semiconductor device is converted to a light/dark signal and overlaid on a displayed image of the semiconductor device (in similar fashion to that described herein above with respect to Cole '305) to indicate the state of the sensed voltage across the semiconductor as a function of the position of the scanning beam's position. The technique employed by Cole '305 is commonly referred to as TIVA (Thermally Induced Voltage Alteration).
Still another example of a prior art technique is given by U.S. Pat. No. 5,952,837, “Scanning Photoinduced Current Analyzer Capable of Detecting Photoinduced Current in Nonbiased Specimen”, issued Sep. 14, 1999 to Koyama (hereinafter “Koyama”). Similar to Cole '183, Koyama uses a laser-scanning microscope (LSM) to image and thermally stimulate conductors of a semiconductor device. Unlike Cole '183, however, Koyama senses only currents produced by thermoelectromotive force produced by the Seebeck effect in response to localized heating of conductors of a semiconductor device. The Koyama technique is intended primarily to locate voids underlying conductors of an integrated circuit, the theory being that conductors overlying voids will rise in temperature to greater degree than conductors overlying solid material, thereby producing a resistance increase corresponding to the rise in temperature. A current amplifier is used to detect Seebeck effect currents produced during scanning. The detected current is converted to a light/dark signal and overlaid upon a displayed image of the semiconductor device to produce a visual indication of the location of buried voids and other similar defects in the semiconductor device. This technique is often referred to as “OBIRCH” (Optical Beam Induced Resistance Change).
Cole '305, Cole '183 and Koyama all operate on either a statically biased or unbiased DUT (Device Under Test). The interaction of the scanning beam (e.g., LSM) induces either a voltage or current change that is sensed, amplified, and finally overlaid with a Laser Scanning Microscope(s) confocal or reflected light image. In each case, the response of the device under test is recorded versus scanner position to produce an image. Nominally, the recording and display techniques of Cole '305, Cole '183 and Koyama require an analog to digital (A/D) conversion, a general-purpose computer and a monitor.
These techniques and other similar techniques are used to detect defect excursions, diagnose their root sources, and to aid an operator in determining appropriate corrective action. Such techniques can be collectively referred to as physical failure analysis, or PFA. Traditionally, PFA is performed on semiconductor devices at a dedicated PFA laboratory away from the semiconductor device's point of fabrication (the semiconductor “fab”). Typically, PFA laboratories are equipped with a wide variety of complex analytical equipment for diagnosing semiconductor device problems. When a defect excursion cannot be resolved by standard in-fab (i.e., at the point of fabrication) inspection and review procedures, samples of the defective product wafers are taken from the fab to the PFA laboratory, where they are extensively tested (and typically never returned). This process introduces costly delays into the analysis cycle and requires the sacrifice of an entire wafer to characterize defects, whose root cause usually involves only a few small, isolated elements of a single semiconductor device on the wafer.
Cole '305, Cole '183, Koyama and other similar PFA techniques generally assume the practicality of biasing a semiconductor device (DUT) with a constant voltage or current source in a manner such that the DUT can be configured or exercised to put it into a known or measurable failing state. For slow timing and low static power devices this is often feasible. However, when high power and/or high frequency excitation are necessary, these techniques become inefficient at best, and in most cases inapplicable.
These prior-art PFA techniques (e.g., COLE305, COLE183, KOYAMA) tend to be good at detecting and isolating “hard” static failures such as “Shorts: (Low electrical Resistance) or “Opens: (High Electrical Resistance) in devices but tend not to be useful for detecting and isolating “AC” type critical parameter failure mechanisms (e.g., timing sensitive failures, defects that cause only Vmin or Vmax failures, timing or voltage condition sensitive failures, etc.).